1 ps8698 07/25/03 product features ? r on is 4? typical ? low bit-to-bit skew: 200ps ? low crosstalk: C27db @ 250mhz ? low current consumption: 20a ? near zero propagation delay: 250ps ? switching speed: 9ns ? channel on capacitance: 6pf (typical) ? v cc operating range: +3.0v to +3.6v ? esd>2000v . . . human body model ? >500 mhz bandwidth (or data frequency) ? package (pb-free available): 48-pin 240 mil wide plastic tssop (a) applications ? routes physical layer signals for usb 2.0 1 0 i 1 1 i 1 gnd 0 i 2 1 i 2 gnd 2 i 1 3 i 1 gnd 2 i 2 3 i 2 gnd vdd 4 i 1 5 i 1 gnd 4 i 2 5 i 2 gnd 6 i 1 7 i 1 gnd 6 i 2 7 i 2 vdd y0 gnd y1 gnd vdd gnd y2 gnd y3 gnd vdd gnd nc y4 gnd y5 gnd vdd gnd y 6 gnd y7 sel 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 38 37 36 35 34 48 47 46 45 44 43 33 32 31 30 42 41 40 39 20 21 22 23 24 29 28 27 26 25 product description pericom semiconductors pi3usb series of logic circuits are produced using the companys advanced sub-micron cmos technology, achieving industry leading performance. the PI3USB40 is a 16- to 8-channel multiplexer/demultiplexer usb switch with hi-z outputs. industry leading advantages include a propagation delay of less than 250ps, resulting from its low channel resistance and i/o capacitance. the device multiplexes differential outputs from a usb transceiver device to one of two corresponding outputs. the switch is bidirectional and offers little or no attenuation of the high-speed signals at the outputs. it is designed for low bit-to-bit skew, high channel-to- channel noise isolation and is compatible with various standards, such as high speed usb 2.0 (480 mb/s). logic block diagram pin description PI3USB40 3.3v, wide bandwidth, 8-channel, 2:1, mux/demux usb 2.0 switch with single enable sel y 7 y 6 y 5 y 4 y 3 y 2 y 1 y 0 1i 1 0i 1 1i 2 0i 2 3i 1 2i 1 3i 2 2i 2 5i 1 4i 1 5i 2 4i 2 7i 1 6i1 7i 2 6i 2
2 ps8698 07/25/03 PI3USB40 3.3v, wide bandwidth, 8-channel, 2:1, mux/demux usb 2.0 switch with single enable storage temperature....................................C65c to +150c supply voltage to ground potential...............C0.5v to +4.0v dc input voltage............................................C0.5v to +5.5v dc output current......................................................120ma power dissipation...........................................................0.5w note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and func - tional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. maximum ratings (above which useful life may be impaired. for user guidelines, not tested.) truth table function sel y n to n i 1 l y n to n i 2 h dc electrical characteristics for usb 2.0 switching over operating range (t a = C40c to +85c, v cc = 3.3v 10%) paramenter description test conditions min. typ.(2) max. units v ih input high voltage guaranteed high level 2 - - v v il input low voltage guaranteed low level C0.5 - 0.8 v ik clamp diode voltage vcc = max., iin = C18ma - C0.7 C1.2 i ih input high current vcc = max., vin = vcc - - 5 a i il input low current vcc = max., vin = gnd - - 5 i off power down leakage current vcc = 0v, va = 0v, vb 3.6 - - - r on switch on-resistance (3) vcc = min., 1.5v vin vcc iin = C40ma - 4 8 ? r flat(on) on-resistance flatness (4) vcc = min., vin @ 1.5v and vcc iin = C40ma - 1 - ?r on on-resistance match from center ports to any other port (4) vcc = min., 1.5v vin vcc iin = C40ma - 0.9 2
3 ps8698 07/25/03 PI3USB40 3.3v, wide bandwidth, 8-channel, 2:1, mux/demux usb 2.0 switch with single enable power supply characteristics notes: 1. for max. or min. conditions, use appropriate value specifed under electrical characteristics for the applicable device type. 2. typical values are at v cc = 3.3v, t a = 25c ambient and maximum loading. 3. per ttl driven input (control inputs only); a and b pins do not contribute to i cc . parameter description test conditions min. typ. (2) max. units x talk crosstalk rl = 100?, f = 250mhz - -27 - db o irr off isolation - -32 - bw bandwidth C3db rl = 100? - 500 - mhz notes: 1. for max. or min. conditions, use appropriate value specifed under electrical characteristics for the applicable device type. 2. guaranteed by design. 3. the bus switch contributes no propagational delay other than the rc delay of the on-resistance of the switch and the load capacitance. the time constant for the switch alone is of the order of 0.25ns for 10pf load. since this time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagational delay to the system. propagational delay of the bus switch when used in a system is determined by the driving circuit on the driving side of the switch and its interactions with the load on the driven side. dynamic electrical characteristics over the operating range (t a =-40o to +85oc, v cc =3.3v10%, gnd=0v) parameters description test conditions (1) min. typ. (2) max. units i cc quiescent power supply current v cc = max., v in = gnd or v cc - - 800 a capacitance ( t a = 25c, f = 1mhz) notes: 1. for max. or min. conditions, use appropriate value specifed under electrical characteristics for the applicable device type. 2. typical values are at v cc = 3.3v, t a = 25c ambient and maximum loading. 3. measured by the voltage drop between a and b pins at indicated current through the switch. on-resistance is determined by the lower of the voltages on the two (a & b) pins. 4. this parameter is determined by device characterization but is not production tested. parameters (5) description test conditions typ. max. units c in input capacitance v in = 0v 2.0 3.0 pf c off port i capacitance, switch off 4.0 6.0 c on switch capacitance, switch on 6.0 10.0 paramenter description test conditions min. typ. (2) max. units t pd propagation delay (2,3) - 0.25 ns t pzh , t pzl line enable time - sel to y n , i n 0.5 - 15 t phz , t plz line disable time - sel to y n , i n 0.5 - 9 t sk(o) output skew between center port (y4 to y5) to any other port (2) - 0.1 0.2 t sk(p) skew between opposite transitions of the same output (tphl - tplh) (2) - 0.1 0.2 switching characteristics
4 ps8698 07/25/03 PI3USB40 3.3v, wide bandwidth, 8-channel, 2:1, mux/demux usb 2.0 switch with single enable r t 10pf c l v cc v in v out 200 ? 200 ? 6.0v pulse generator d.u.t test circuit for electrical characteristics (1) notes: 1. c l = load capacitance: includes jig and probe capacitance. 2. r t = termination resistance: should be equal to z out of the pulse generator 3. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. 4. all input impulses are supplied by generators having the following characteristics: prr mhz, z o = 50?, t r 2.5ns, t f 2.5ns. 5. the outputs are measured one at a time with one transition per measurement. switch positions test circuit for dynamic electrical characteristics v cc PI3USB40 t1 r1 s1 hp1 1667a 50 ? 10pf hp4195a test switch t plz , t pzl (output on b-side) 6.0v t phz , t pzh (output on b-side) gnd prop delay open
5 ps8698 07/25/03 PI3USB40 3.3v, wide bandwidth, 8-channel, 2:1, mux/demux usb 2.0 switch with single enable voltage waveforms propagation delay times switching waveforms output skew - t sk(o) pulse skew - t sk(p) voltage waveforms enable and disable times data in data out at channel x data out at channel y t plhx t phlx 3.5v 2.5v 2.5v 2.5v i t sk(o) = i t plhy C t plhx i or i t phly C t phlx i t sk(o) t plhy t phly v oh v ol v ol v oh 1.5v input output t plh t sk(p) = i t phl C t plh i t phl 3.5v 2.5v 2.5v v ol v oh 1.5v t plz 1.25v 1.25v 2.5v v oh 0v v ol v dd/2 v dd/2 t phz t pzl t pzh output output v ol +0.3v v oh C0.3v v ol v oh sel applications information logic inputs the logic control inputs can be driven up to +3.6v regardless of the supply voltage. for example, given a +3.3v supply, the output enables or select pins may be driven low to 0v and high to 3.6v. driving in rail-to-rail? minimizes power consumption. power-supply sequencing proper power-supply sequencing is advised for all cmos devices. it is recommended to always apply v cc before applying signals to the input/output or control pins. rail-to-rail is a registered trademark of nippon motorola, ltd input t plh 2.5v 2.5v 2.5v 2.5v t phl 3.5v 1.5v output v oh v ol
6 ps8698 07/25/03 PI3USB40 3.3v, wide bandwidth, 8-channel, 2:1, mux/demux usb 2.0 switch with single enable packaging mechanical: 48-pin tssop (a) .236 .244 .488 .496 .002 .006 seating plane .007 .010 .0197 bsc .004 .008 .319 1 48 12.4 12.6 6.0 6.2 0.50 0.17 0.27 8.1 0.05 0.15 0.09 0.20 x.xx x.xx denotes dimensions in millimeters .018 .030 0.45 0.75 .047 1.20 max bsc ordering information notes: 1. thermal characteristics can be found on the company web site at http://www .pericom.com/packaging/mechanicals.php ordering code package code package type PI3USB40a a 48-pin 240 mil wide plastic tssop (a) PI3USB40ae a pb-free, 48-pin 240 mil wide plastic tssop (a) pericom semiconductor corporation 2380 bering drive ? san jose, ca 95131 ? 1-800-435-2336 ? fax (408) 435-1100 ? http://www.pericom.com
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